The present invention relates generally to microprocessors, and more particularly, to an efficient implementation of multiprecision arithmetic.
Reduced Instruction Set Computing (RISC) microprocessors are well-known. RISC microprocessors are characterized by a smaller number of instructions, which are relatively simple to decode, and by requiring that all arithmetic/logic operations be performed register-to-register. RISC instructions are generally of only one length (e.g., 32-bit instructions). RISC instruction execution is of the direct hard-wired type, as opposed to microcoding. There is a fixed instruction cycle time, and the instructions are defined to be relatively simple so that each instruction generally executes in one relatively short cycle.
A RISC microprocessor typically includes an instruction for performing multiprecision arithmetic. However, a typical multiprecision add instruction or multiprecision subtract instruction is implemented using a condition code register. FIG. 1 illustrates an implementation of a multiprecision add operation in a typical microprocessor. FIG. 1 shows an n-bit adder 100 that can perform an addition operation and a subtraction operation. The add/sub control wire is set to zero for addition, which allows for the Y vector to be applied unchanged to one of the adder inputs along with a carry-in signal, C0. When the add/sub control wire is set to one, indicating subtraction, the Y vector is 1""s complemented (that is bit complemented), and C0 is set to 1 to complete the 2""s complementation of Y. When adding unsigned numbers, the carry-out Cn serves as the overflow indicator. FIG. 1 also shows a condition code register 102 that includes a carry bit 104 which functions as a condition code flag. The condition code flag provides the carry-out signal Cn of the n-bit adder 100. The condition code flag is set to 1 if a carry-out results from an add operation, otherwise the condition code flag is set to 0. Additionally, the condition code flag is set to 1 if no carry-out results from a subtract operation, otherwise the condition code flag is set to 0.
An important aspect of condition code flags generally is the role of the C (Carry) flag in performing multiprecision (multiple-precision) arithmetic. For example, consider adding two operands, X and Y, each occupying several words in memory. The addition can be performed by a program loop that adds individual words in successive iterations. The C flag must be preserved from one iteration to the next in order to propagate the carries through the complete addition operation.
However, it is desirable to eliminate condition codes in the architecture of a microprocessor.
An efficient implementation of multiprecision (multiple precision) arithmetic is provided. For example, an implementation of multiprecision arithmetic is provided that eliminates condition codes, such as condition codes for a carry bit and a borrow bit, and eliminates an add-with-carry instruction for multiprecision addition and a subtract-with-borrow instruction for multiprecision subtraction. In one embodiment, the present invention provides a cost-effective and high performance implementation of multiprecision arithmetic execution on a microprocessor.
In one embodiment, a method for multiprecision arithmetic, includes executing an add instruction, the add instruction adding a first operand and a second operand, and executing a generate carry instruction, the generate carry instruction generating the carry for addition of the first operand and the second operand.
In one embodiment, a method for multiprecision arithmetic, includes executing a subtract instruction, the subtract instruction subtracting a first operand and a second operand, and executing a generate borrow instruction, the generate borrow instruction generating the borrow for subtraction of the first operand and the second operand.